Project Statistics |
PROP_Enable_Message_Filtering=true |
PROP_FitterReportFormat=HTML |
PROP_ImpactProjectFile=changed |
PROP_LastAppliedGoal=Timing Performance |
PROP_LastAppliedStrategy=Performance without IOB Packing;/opt/Xilinx/13.2/ISE_DS/ISE/spartan3/data/spartan3_performance_without_iobpacking.xds |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store all values |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthOptEffort=High |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserBrowsedStrategyFiles=/opt/Xilinx/13.2/ISE_DS/ISE/spartan3/data/spartan3_performance_with_physicalsynthesis.xds |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2013-05-23T19:37:57 |
PROP_intWbtProjectID=4F4636A063B22F172BF344B1410E168F |
PROP_intWbtProjectIteration=50 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_xilxMapAllowLogicOpt=true |
PROP_xilxMapCoverMode=Speed |
PROP_xilxMapTimingDrivenPacking=true |
PROP_xilxPARplacerEffortLevel=High |
PROP_xilxPARrouterEffortLevel=High |
PROP_xilxSynthRegBalancing=Yes |
PROP_xstPackIORegister=No |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3 |
PROP_MapLogicOptimization=true |
PROP_MapRegDuplication=On |
PROP_DevDevice=xc3s1000 |
PROP_DevFamilyPMName=spartan3 |
PROP_MapExtraEffort=Normal |
PROP_xilxPARextraEffortLevel=Normal |
PROP_DevPackage=ft256 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=Verilog |
FILE_COREGEN=1 |
FILE_UCF=1 |
FILE_VERILOG=14 |
FILE_XAW=1 |