Using the PICPLD Bootloader

Versions of the PICPLD shipped after 16 January 2004 have a built-in PIC boot loader. This boot loader allows you to program the onboard PIC without an external PIC programmer. If you have a PIC programmer and would prefer to use it, you can simply erase the chip (that is, program over the boot loader with your programmer) and use the chip as an ordinary PIC. However, if you don't have a PIC programmer, or you'd like to use the efficient bootloader, you can download code to the PIC over the PICPLD's RS232 port using practically any operating system.

The PICPLD boot loader does consume some PIC resources. In particular, you only have 3.8K of program space (that is, the boot loader take about 256 instructions). It also prevents you from using the RTS handshaking line in your own program.  In addition, the bootloader provides the same services as our APP-II boot loader (see our APP-II resource page). Note that the boot loader programs will not work with the PICPLD boot loader but you can use the APP2.INC and even run the demo programs.

Here's how to download a program to the PICPLD bootloader:

1. Prepare your HEX file in the usual way.

2. The PICPLD senses RTS to tell if it should load a program or run the previously loaded program. So if you open a terminal program (19200 baud, 8 bits, 1 stop bit, no pairty, hardware handshaking) and reset the PIC, it will enter load mode (indicated by a > character on the terminal screen).

3. Use ASCII transfer to send your HEX file to the PIC. When successful the PIC will send a ! character and wait for you to reset it.

4. To run the program, disconnect the terminal program so that RTS is no longer asserted. Then reset the processor.

If you are using Windows Hyperterminal, you can press Connect when you are ready to program and then press Disconnect when you want to run the program. It is that simple.

If the RS232 cable is disconnected, the program will run. In addition, the RTS line is only sampled on start up, so you must be sure that RTS is not asserted when the processor resets during normal operation.